1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more specifically, to semiconductor memory devices comprising memory chips mounted on printed circuit boards and operating method thereof.
2. Description of the Prior Art
Recently, IC (Integrated Circuit) cards have been remarkably developed. One type of such IC cards is a memory card comprising a memory (not containing a CPU) such as a static RAM, a programmable ROM, and so on.
In general, a memory used in such a memory card is adapted to be accessed only sequentially but not randomly. On the other hand, in a conventional magnetic disc memory, for example, any one of sectors formed in the disc is selected by random accessing while data can be accessed only sequentially within the selected sector. Therefore, the above described memory card can be adapted to the same use as that of the conventional magnetic disc memory.
FIG. 1 is a block diagram schematically showing the structure of such conventional IC card (memory card). Referring to FIG. 1, an integrated circuit 1 having a memory circuit 2 formed of a known SRAM, PROM, EPROM or a mask ROM mounted thereon is provided in a package 100 of the IC card. The integrated circuit 1 has n address terminals 3 connected to the memory circuit 2 for receiving n bits of address signals A.sub.1, A.sub.2, . . . , A.sub.n and m data terminals 4 connected to the memory circuit 2 for inputting/outputting m bits of data D.sub.1, D.sub.2, . . . , D.sub.m. Further, n external address terminals 5 and m external data terminals 6 are provided in the package 100, with the address terminals 3 of the integrated circuit 1 respectively connected to the corresponding external address terminals 5 by printed wires and the data terminals 4 respectively connected to the corresponding external data terminals 6 by printed wires. These external address terminals 5 and the external data terminals 6 are provided for communication with an interface circuit (not shown) on the side of the terminal equipment, when the IC card is inserted in the terminal equipment (not shown) More specifically, when these external terminals 5 and 6 are coupled to the interface circuit of the terminal equipment, n bits address signals A.sub.1, A.sub.2, . . . , A.sub.n applied from the interface circuit to the external address terminal 5 are further applied to the memory circuit 2 through the address terminals 3 of the integrated circuit 1, thereby accessing any one of the memory cells (not shown) constituting the memory circuit 2. The exchange of data between the selected memory cell and the interface circuit of the terminal equipment is carried out through the external data terminals 6 and the data terminals 4 of the integrated circuit 1.
FIG. 2 is a block diagram schematically showing another structure of a conventional IC card (memory card). Although only one integrated circuit 1 (one memory circuit 2) is provided in the IC card of FIG. 1, a plurality of integrated circuits (memory circuits) may be formed on the IC card. As an example of such IC cards, FIG. 2 shows an IC card having two integrated circuits. Referring to FIG. 2, two integrated circuits 1a and 1b having two memory circuits 2a and 2b respectively are provided in the package 100 of the IC card. The integrated circuit 1a includes n address terminals 3a and m data terminals 4a while the integrated circuit 1b includes n address terminals 3b and m data terminals 4b, as in the integrated circuit 1 of FIG. 1. Similarly, n external address terminals 5 and m external data terminals 6 are provided in the package 100. Respective address terminals of the integrated circuits 1a and 1b are commonly connected to the corresponding external address terminals 5, and the respective data terminals are commonly connected to the corresponding external data terminals 6.
However, these integrated circuits 1a and 1b are different from the integrated circuit 1 of FIG. 1 in that these integrated circuits 1a and 1b comprise output enable terminals 7a and 7b connected to respective memory circuits 2a and 2b. Namely, two external output enable terminals 8a and 8b are provided in the package 100. One terminal 8a is connected to the output enable terminal 7a of the integrated circuit 1a and the other one 8b is connected to the output enable terminal 7b of the integrated circuit 1b. When the said IC card is inserted into the terminal equipment (not shown) and respective output terminals 5, 6, 8a and 8b are coupled to the interface circuit (not shown) of the terminal equipment, a signal selecting either the integrated circuit 1a or 1b is supplied to the external output enable terminals 8a and 8b from the interface circuit. More specifically, signals having different logic levels are applied to the output enable terminals 7a and 7b of the integrated circuits 1a and 1b and, as a result, the data terminals of one of the integrated circuits 1a and 1b are brought to the output state while the data terminals of the other one of the integrated circuits 1a and 1b are brought to the high impedance state. Namely, in effect, only the data terminals of the selected integrated circuit are connected to the external data terminals 6, and therefore, either one of the integrated circuits can be selected by changing the signals applied to the external output enable terminals 8a and 8b. As described above, in the conventional IC card shown in FIG. 2, the memory capacity can be enlarged without increasing the number of external address terminals 5 and the external data terminals 6.
However, in the IC cards shown in FIGS. 1 and 2, n external address terminals 5 are still necessary for inputting n bit address signals. The number of the external address terminals 5 is, for example, 20 when the memory capacity of the memory circuit 2 of FIG. 1 is 1 Mword. The number of necessary external address terminals 5 increases as the capacity of the memory circuit 2 itself is increased. Preferably, the number of external terminals should be smaller and the size of the external terminal should be large, in order to prevent defects in contact and to facilitate manufacturing and processing. Therefore, when the number of external terminals are increased as described above, the IC card itself becomes large. When the size of the terminal is made small to reduce the size of the card, the processing requires high precision, so that the IC card becomes expensive, and, at the same time, malfunctions such as defective contact are likely to occur.
Meanwhile, FIG. 3 is a block diagram schematically showing a conventional logic large scale integrated circuit (logic LSI) with a memory circuit which is operable in a test mode. Such logic LSI is disclosed in, for example, "DESIGNING DIGITAL CIRCUITS WITH EASILY TESTABLE CONSIDERATION" by S. Funatsu et al., 1978 SEMICONDUCTOR TEST CONFERENCE, DIGEST OF PAPERS, Pages 98 to 102. More specifically, referring to FIG. 3, a test address signal is serially applied to a terminal 110 while a serial clock signal is applied to a terminal 120 in a test environment. A shift register 130 converts the received serial address signal to parallel data to output the same. A switching circuit 140 selects the parallel data to apply the same to address inputs of a memory circuit 150 in the test mode. As a result, address to be tested in the memory circuit 150 is designated to perform testing operation. On the other hand, in a normal mode, an address signal from a logic circuit 160 is selected by the switching circuit 140 to be applied to the memory circuit 150, so that data transfer is performed between the memory circuit 150 and the logic circuit 160. As described above, in the conventional logic LSI having test function, a shift register for converting serial address input into parallel data may be provided.
However, this shift register in the logic LSI shown in FIG. 3 is provided only for the purpose of providing test addresses in the test mode and the technique shown in FIG. 3 suggests nothing about the particular use of the shift register to reduce the number of external terminals in a memory card wherein only sequential accessing is possible.
In addition, according to the shift register shown in FIG. 3, in the test mode, a plurality of shift operations are necessary to set one address, so that speed of accessing of the memory circuit can not be increased.